For more than three decades, the continued miniaturization of silicon metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. A concise summary of near-term and long-term challenges to continued CMOS scaling can be found in the “Grand Challenges” section of the 2002 Update of the International Technology Roadmap for Semiconductors (ITRS). A very thorough review of the device, material, circuit, and systems can be found in Proc. IEEE, Vol. 89, No. 3, March 2001, a special issue dedicated to the limits of semiconductor technology.
Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, methods for improving performance without scaling have become critical. One approach for doing this is to increase carrier (electron and/or hole) mobilities. Increased carrier mobility can be obtained, for example, by building MOSFETS on Si surfaces that are orientated in directions different than conventional (100) Si. For example, the (100) crystal surface provides n-type field effect transistors (nFETs) with high performance, while the (110) crystal surface provides p-type field effect transistors (pFETs) with high performance.
Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2×-4× lower than the corresponding electron hole mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching. PFETs having larger widths are undesirable since they take up a significant amount of chip area.
On the other hand, hole mobilities on (110) Si are approximately 2× higher than on (100) Si; therefore, pFETs formed on a (110) surface will exhibit significantly higher drive currents than pFETs formed on a (100) surface. Unfortunately, electron mobilities on (110) Si surfaces are significantly degraded compared to (100) Si surfaces.
Prior attempts to provide substrates having multiple orientations have not provided planar silicon-on-insulator (SOI) substrates for both nFET and pFET devices. SOI substrates are advantageous over bulk-Si substrates, since SOI substrates reduce parasitic capacitance within the integrated circuit and reduce individual circuit loads, thereby improving circuit and chip performance.
In view of the above, there is a need for providing integrated semiconductor devices that are formed upon a planar SOI substrate having different crystal orientations that provide optimal performance for a specific device. That is, there is an overwhelming need to create a planar SOI substrate which allows one type of device, such as, for example, a pFET, to be formed on a certain crystallographic surface, e.g., a (110) surface, while forming another type of device, such as, for example, an nFET, on another crystallographic surface, e.g., a (100) surface.